1. Field of Invention
The present invention relates to a refresh controller in semiconductor memory that controls the refresh cycle of a memory cell array.
2. Discussion of Related Art
Memory cells in DRAM should, ideally, be arranged as a square matrix. Accordingly, a specific cell may be selected by decoding 24 address bits wherein half of the address bits are to identify a row and the other half of the address bits are to identify a column. Since each number of the row address bits and column address bits are 12, it is possible to reduce the external address pins to 12 by supplying the row address signals and the column address signals alternately through the 12 external address pins. This is called address multiplexing, which simplifies the packaging process.
For the address multiplexing above mentioned, an address latch is required for separation of the row address bits and the column address bits. Additionally, a row address strobe signal/RAS, indicating the row address input, and a column address strobe signal/CAS, indicating the column address input, are also required for the address multiplexing.
Accordingly, a function that synchronizes the input of the row address and the column address with the row address strobe signal/RAS and the column address strobe signal/CAS, respectively, is required. And, a row address latch and a column address latch are also required also.
According to this, in 16 M DRAM, address pins are reduced from 24 to 13. 12 pins are for the address signals and the other pin is for the column address strobe signal. The row address signal is sent over the chip enable signal pin. Thus, no additional pins are required for the row address strobe signal.
The row address signal and the column address signal are inputted from the address pins to internal circuitry at a certain time interval. The initial input path to the row address decoder and column address decoder is same. However, the decoding stage is divided into multiple stages such as predecoding and main decoding as the number of address bits increase.
There are two different ways of separating the input path of the row address signal and the column address signal. One way is to separate them after being stored in an address buffer. The other way is to separate them right before the predecoder, and, in this case, the input path of the row address signal and the column address signal share the address buffer. For 16 M DRAM and higher, the way of separating the input path of the row address signal and the column address signal before the row address buffer and column address buffer can be generalized.
Refresh operation in DRAM is carried out when the row address strobe signal is "low" level and after a refresh address is inputted. This is called `RAS Only Refresh`.
Such refresh operation has to be done before the cell capacitor is discharged and unable to indicate whether data is logic "1" or "0". This critical time is called a refresh period.
A refresh cycle is defined as the number of times required to complete refresh of all memory cells in memory cell array. The refresh period divided by the refresh cycle gives the refresh interval. This refresh interval determines a time interval of each refresh cycle so that the refresh operation is executed at regular intervals.
There are many different kind of refresh operations in a DRAM such as automatic refresh, hidden refresh, self refresh and the like.
In 64 K DRAM, a refresh signal is applied to a spare pin. This refresh signal determines the acceptance of the internal address. Namely, if the refresh signal is activated (i.e. low level) prior to the row address strobe signal, the refresh operation in following cycles is carried out using the internal address, and an external address is ignored. After the refresh operation for a wordline is finished, the internal address counter counts up 1 bit for the next refresh cycle. Thus an external refresh counter is not necessary.
There is another way of refresh control which uses abnormal operation of a DRAM. So-called CAS before RAS (CBR) refresh, a type of automatic refresh, is an example of this kind of refresh control. Instead of the refresh signal, the column address strobe signal is activated prior to the row address strobe signal (i.e. CAS before RAS). A refresh controller regards the abnormal operation as the refresh signal, and this eliminates the need for a signal pin. In this case, a built-in internal address counter generates internal addresses used to refresh, and an external address is ignored.
In order to make CBR refresh effective, the column address strobe signal needs to be activated at a time tCSR(/CAS set up time) prior to the row address strobe signal and maintained for at least an amount of time tCHR(/CAS hold time).
FIG. 1 is a block diagram that shows a conventional address input stage connected to a memory cell array in semiconductor memory.
As shown in FIG. 1, the address input stage has a row address latch 103 and a column address latch 105 within the address input buffer 101. The row address is stored in row address latch 103 and the column address is stored in column address latch 105. These stored addresses are decoded by decoder to select a memory cell to read or write data.
The TTL level external address signal of 12 bits is inputted to the address input buffer 101 through an address input pad. The address input buffer 101 converts the external address signal TTL to the CMOS level external address signal EXT.sub.-- A'.
The external address signal EXT.sub.-- A is comprised of the external row address signal EXT.sub.-- AX and the external column address signal EXT.sub.-- AY. These two external address signals EXT.sub.-- AX and EXT.sub.-- AY are output from the address input buffer 101 alternately. The converted external row address signal EXT.sub.-- AX is stored in the row address latch 103, and the converted external column address signal EXT.sub.-- AY is stored in the column address latch 105.
An internal address counter 102 receives the refresh signal REF. When the refresh signal REF is activated to high level, the internal address counter 102 generates an internal address signal INT.sub.-- AX[11:01], which is supplied to the row address latch 103. In this case, the internal address signal INT.sub.-- AX is an internal `row` address signal.
As above mentioned, the internal address signal INT.sub.-- AX and the external row address signal EXT.sub.-- AX are latched in the row address latch 103. In addition, the refresh signal REF and the wordline driving signal ACT are also supplied to the row address latch 103.
The row address latch 103 latches the internal address signal INT.sub.-- AX when the refresh signal REF is activated to high level, and latches the row address signal EXT.sub.-- AX when the wordline driving signal ACT is activated to high level.
A row predecoder 104 receives and predecodes the internal address signal INT.sub.-- AX stored in the row address latch 103 or the row address signal EXT.sub.-- AX.
The predecoding operation in the row predecoder 104 will now be described.
The row predecoder 104 generates two block address signals BX0 and BX1 by decoding the most significant bit of the internal address signal INT.sub.-- AX or the most significant bit of row address signal EXT.sub.-- AX. Each block address signal BX0 and BX1 selects two of four cell blocks. The entire memory cell array is divided into plural cell blocks, and each cell block is designated by a unit address input.
The remaining bits of the internal address signal INT.sub.-- AX or the row address signal EXT.sub.-- AX are the actual row address signal AX for selecting a single wordline in the cell block selected by the block address signals BX0 and BX1.
Every cell block 107 has its own row decoder 108 as a main decoder. The row decoder 108 receives one bit of the two block address signals BX0 and BX1 and the predecoded row address signal AX. Thus the row decoder 108 is selected by the block address signals BX0 and BX1. The selected row decoder 108 decodes the row address signal AX to select a corresponding wordline.
The column address latch 105 receives a read/write signal RD/WT and also receives the external column address signal EXT.sub.-- AY from the input buffer 101. The column address latch 105 latches the column address signal EXT.sub.-- AY when the read/write signal RD/WT is activated.
The external column address signal EXT.sub.-- AY in the column address latch 105 is supply to the column predecoder 106. The column predecoder 106 generates the column address signal AY by predecoding the column address signal EXT.sub.-- AY. The column decoder 109 decodes the predecoded column address signal AY to select the corresponding bitline. Every cell block 107 has a sense amplifier 110. The sense amplifier 110 is activated by decoded column address AY and carries out read/write and refresh operations. Each sense amplifier controllers 111, indicated by SAC in FIG. 1 and associated with a sense amplifier 110, generates a read/write control signal and a refresh control signal to control the sense amplifier 110.
FIG. 2 shows a timing diagram of the address input stage in FIG. 1, and in particular, a timing diagram of the refresh operation using the internal address signal INT.sub.-- AX. In FIG. 2, the internal address signal INT.sub.-- AX is generated by the activated refresh signal REF. The actual row address is taken from the decoded internal address signal INT.sub.-- AX. Assuming that the row address signals AXk and AXn are generated, two wordlines WLk and WLn are selected.
These two selected wordlines WLk and WLn are in separate cell blocks. Since two cell blocks are selected by the unit row address, just one wordline corresponding the unit row address is selected and activated in each selected cell block. If the memory cell array has more cell blocks (i. e. more cells), higher power consumption will occur. And, since this refresh capability is not enough to refresh a highly integrated memory, the refresh failure rate increases.
Generally, a defective memory cell is repaired by an available redundant memory cell. But, there is a limitation on redundancy in semiconductor memory. Thus, only an extremely defective memory cell is repaired by a redundant memory cell.
A refresh defect means that a memory cell requires more refresh current or a longer refresh period than a normal cell due to larger leakage current than a normal cell. In other words, a refresh defect memory cell is a memory cell which has refresh defects. Since defective cells (i.e. refresh defective cells) require more current to be refreshed than normal cells, refresh time is determined by defective cells. But, in fact, there are more normal cells than defective cells in a memory cell array. Thus, determining the refresh timing based on defective cells is very inefficient from a standpoint of power consumption.